The present invention is related to a clock circuit for use in a general purpose digital computer, and is more particularly related to a clock distribution system for distributing a clock signal to a plurality of circuit boards of a digital computer.
Because of the sizes of circuits and cabinets generally used for a general purpose digital computer, it is many times desirable to utilize several circuit boards to support the complete system. Clock distribution systems are known for distributing clock pulses to the circuit boards to synchronize the components of the digital computer. Because of the difference of the times of propagation of the various elements of a clock distribution system for high-to-low and low-to-high transitions, the pulse widths of a clock signal are distorted by each element through which the clock signal passes. When a logic tree of many stages of transistor-to-transistor logic (TTL) devices is used for a clock distribution system, the distortion and skew of clock pulses is such that the clock pulses are not usable for a digital computer system, expecially for very large scale integrated (VLSI) circuit chips.
U.S. Pat. No. 3,739,199 issued June 12, 1973 to Negrou for "Generator Of A Time Interval As A Multiple Of A Base Period" discloses a device having a standard time interval of a well-defined duration delimited by two fronts separated by N periods of an oscillation.
U.S. Pat. No. 3,921,079 issued Nov. 18, 1975 to Heffner et al. for "Multi-Phase Clock Distribution System" discloses a multi-phase clock distribution system utilizing a phase shift adjustment circuit in each phase clock chain preceeding a phase output countdown circuitry thereby providing phase adjustability which is inherently free from period, pulse width or edge distortion and produces clock signals with precisely determined leading and trailing edges.
Other patents which show the state of the art include: U.S. Pat. No. 3,124,705 issued Mar. 10, 1964 to Gray, Jr. for "Synchronized Single Pulse Circuit Producing Output of Predetermined Length From Delay Lines Having Dissimilar Periods"; U.S. Pat. No. 3,675,049 issued July 4, 1972 to Haven for "Variable Digital Delay Using Multiple Parallel Channels And A Signal-Driven Bit Distributor"; U.S. Pat. No. 4,063,109 issued Dec. 13, 1977 to van der Mark for "Clock Pulse System"; U.S. Pat. No. 4,253,065 issued Feb. 24, 1981 to Wyman et al. for "Clock Distribution System For Digital Computers"; U.S. Pat. No. 4,481,575 issued Nov. 6, 1984 to Bazlen et al. for "Arrangement In A Data Processing System To Reduce The Cycle Time"; and U.S. Pat. No. 4,490,821 issued Dec. 25, 1984 to Lacher for "Centralized Clock Time Error Correction System."